(1) Field of the Invention
The Invention relates to a high-density non-volatile memory device using Twin-MONOS structure, and its fabrication method.
(2) Description of the Prior Art
An insulator charge storage device is a type of non-volatile memory in which charge is stored within the traps of an insulator material. Electrons may be injected into the insulator by either channel hot electron (CHE) or tunneling. Electrons are usually eliminated via some type of hole injection mechanism in a MONOS device contrasting to FN ejection in a floating gate silicon device. In a MONOS device, nitride is the storage element. When the bottom oxide is as thin as or less than 23 Angstroms, holes are injected by a direct tunneling mechanism (S. Minami et.al., “A Novel MONOS Cycles”, IEEE Transactions on Electron Device, VOL.40, No. 11, November 1993, p.p. 2011-2017 and E. Suzuki, Y. Hayashi et.al., “Hole and Electron Current Transport in Metal-Oxide-Nitride-Oxide-Silicon Memory Structures”, IEEE Transactions on Electron Device, VOL.36, No.6, June 1989, p.p. 1145-1149) and the electron negative charge is neutralized by the holes. When the bottom oxide is thicker than 30 Angstroms, high energy hot holes are generated by band to band or avalanche breakdown; these holes are injected into the storage area and recombine with the electrons to neutralize the charge. (T. Y. Chan, Chenming Hu et.al. “A True Single-Transistor Oxide-Nitride-Oxide EEPROM Device” IEEE Electron Device Letters, VOL. EDL-8, No.3, March 1987, p.p. 93-95).
Hot hole injection is notorious for damaging oxide through injection because its effective mass is three times larger than an electron's (Paulo Cappelletti et.al. “Flash Memories” Kluwer Academic Publishers 1999, p.p. 217-223). This damaged oxide creates traps and reduces retention time. The retention time degradation increases as program/erase by hole cycle increases. (FIG. 1)
In his paper, K. T. Chang et.al. “A New SONOS Memory Using Source-Side Injection for Programming” IEEE Electron Device Letters, VOL. 19, No.7, July 1998, p.p. 253-255, the author uses a split gate in an attempt to eliminate the trapped electrons by electric field applying positive bias on the top polysilicon gate (FN erase) instead of hole injection and to avoid hole damage and to improve retention time. However this approach in sidewall split gate structure where the nitride layer is sandwiched between two polysilicon gates encounters the following problem.
FIG. 2 illustrates word gate 20 and control gate 22. Horizontal and vertical components of the ONO nitride 21 are designated as a storage element and an insulator between the two polysilicon gates. The corner component is off the control gate and is less controlled by the gate. A small number of electrons accumulate at the gap nitride 22 between the two-polysilicon gates 20 and 24 at every program erase cycle. In order to eject the electrons trapped in the SiN, a positive bias is applied on the control gate polysilicon 22 while the substrate silicon 10 is grounded. Since the electric field at the gap is weaker compared to the area immediately under the control gate, it is difficult to eject the electrons trapped at the gap. FIG. 4 shows electrons 29 trapped in the nitride 21. Thus the erased state threshold shifts up as the number of program/erase cycles increase, and the window between program and erase states gets smaller. There is a reliability issue associated with the split gate approach. This is illustrated graphically in FIG. 3 where lines 31 and 33 show threshold voltages of programmed and erased cells, respectively, as a function of number of cycles.
U.S. Pat. No. 6,498,377 to Lin et al describes a MONOS cell structure where nitride storage lies under sidewall spacers. U.S. Pat. No. 6,356,482 to Derhacobian et al teaches applying a negative gate erase voltage to improve erase after many program-erase cycles. U.S. Pat. No. 6,040,995 to Reisinger et al discloses F-N tunneling erase of nitride through a thick oxide layer. U.S. Pat. 5,408,115 to Chang shows F-N tunneling erasure through the top oxide wherein the bottom oxide is thick.
A Twin MONOS individual cell structure splitting the gate into one word gate and two control gates on the word gate sidewalls was introduced in U.S. Pat. No. 6,255,166, by Seiki Ogura. Its fabrication method is described in U.S. Pat. No. 6,531,350 also by Seiki Ogura et al. This invention also refers to an array structure of 4 bit-1 contact described in U.S. Pat. No. 6,469,935 by Y. Hayashi et al, where 4 memory storage cells share one contact. This invention still also refers to a simplified fabrication method described in U.S. Provisional Patent Application Ser. No. 60/363,448, filed on Mar. 12, 2002, (docket number Halo02-001), by K. Satoh et al.
The diffusion bit TWIN-MONOS array provided in U.S. Pat. No. 6,255,166 contains two serious concerns. The ONO composite film is deposited after defining the memory word gate followed by the control gate process. Vertical ONO along the word gate sidewall and horizontal ONO overlying the substrate form the L-shaped ONO. There is a gap at the corner of the L-shape between the control gate and the nitride edge. This may make it more difficult to pull the electrons stored in the corner. The electrons stored in the corner nitride are accumulated during program and erase cycles so that the operation window gets narrower as time goes on.
Another concern is the negative slope opening for defining the word line. The word line mask 28 is patterned over the polysilicon line 26′ overlying the polysilicon line 20′ as shown in FIG. 5A. The polysilicon 26′ and 20′ not covered by the word line mask 28 should be etched out. The line 26′ has a positive slope but it becomes a negative opening for etching as shown in FIG. 5B. It is difficult to etch out the polysilicon under the negative opening, as shown by poly residuals 23. It would easily cause word line to word line short and word line to control gate short.